ASIC EDA tools
Synthesis issues and
constraints
Clock routing aspects
and optimization
Critical path analysis
(false paths , multi cycle paths)
Schematic entry and ASIC
simulation
Timing aspects and power
analysis
Layout entry for CMOS
designs
DRC for CMOS submicron
and nanometer technologies
LVS for CMOS based
designs (130 nm examples)
Understanding the
process models and model files
Power analysis for
complex ASIC designs
Low power design
techniques – An overview
Miniproject (schematic,
layout, DRC, LVC, simulation, timing and power analysis)
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